Thin film transistor and fabricating method thereof

ABSTRACT

Thin film transistors and methods of fabricating thin film transistors having low OFF state leakage current. The OFF state leakage current reduction is achieved by using doping implantation energies such that the average penetration depth of the doping impurity into the semiconductor, the projected range Rp, is located below the surface of the semiconductor layer, and such that the concentration of impurities remaining at the surface of the semiconductor layer is relatively small.

[0001] This application claims the benefit of Korean Patent ApplicationNo. 1999-47530, filed on Oct. 29, 1999, which is hereby incorporated byreference for all purposes as if fully set forth herein.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to thin film transistors. Moreparticularly, it relates to thin film transistors that are particularlyuseful as switching devices in liquid crystal displays, and to methodsof fabricating such thin film transistors.

[0004] 2. Discussion of the Related Art

[0005] Active layers of thin film transistors (hereinafter abbreviatedTFTS) are formed on substrates. Such active layers include source anddrain regions comprised of impurity doped materials and an undopedchannel region. Impurity doping means that impurities are implanted intoa substrate layer.

[0006] Impurities in source and drain regions tend to gather near thechannel region when an ON signal is applied to a gate electrode locatedadjacent the active layer, thereby providing a path through whichcarriers can more easily pass.

[0007] To dope a semiconductor layer, doping impurities are acceleratedusing an acceleration voltage to kinetic energies in the range of 1 kVto 10 MV. The accelerated impurities are then directed onto a surface ofa semiconductor. The accelerated impurities contact crystal lattices ofthe semiconductor and transfer their kinetic energy to those lattices.The doping impurities achieve an average penetration depth into thesemiconductor that is referred to as the projected range (hereinafterabbreviated Rp).

[0008] While the projection range is a useful measure of the averagepenetration depth of the impurities, not every impurity locates at theprojection range. Referring now to FIG. 1, doping impurities typicallydistribute with an impurity concentration profile that is almostsymmetrically centering around the projected range Rp. The impurityconcentration profile generally follows a Gaussian distribution having amaximum impurity concentration at Rp. FIG. 1 also illustrates a measureof a distributional deviation called ARp.

[0009]FIG. 2 and FIG. 3 present various illustrations of a related artTFT. FIG. 2 illustrates a cross-sectional view of that related art TFT,while FIG. 3 presents a graph of doping impurity concentration versusdepth (into a semiconductor layer) of that related art TFT. Referringnow to FIG. 2, a semiconductor layer 21 is formed on a buffer layer 20that is over a substrate 200. Over the center of the semiconductor layeris a gate insulating layer 22 that is covered by a gate electrode 23. Atone side of the semiconductor layer 21 is a source region 21S that isdoped with impurities, while the other side of the semiconductor layerhas a drain region 21D that is also doped with impurities. Below thegate insulating layer 22 is an undoped channel region 21C.

[0010] To fabricate the related art TFT illustrated in FIGS. 2 and 3,impurity doping is carried out by accelerating doping impurities suchthat Rp is located less than 100 Å from the surface of the semiconductorlayer 21. Thus, the source and drain regions 21S and 21D are formed, asshown FIG. 3, by heavily doping the surface of the semiconductor layer21 with impurities.

[0011] Unfortunately, TFTs according to FIGS. 2 and 3 tend to have highleakage currents due to the high doping impurity concentrations at ornear the surface of the semiconductor layer when the TFT is in the OFFstate. This leakage current is produced by current flow generated bycarriers in the drain region when an electric field exists between thedrain and gate electrode when the TFT is OFF. One approach to theproblem of high leakage current is to incorporate an offset regionbetween the gate and drain to reduce the electric field, the so-calledlightly-doped-drain (LDD) structure. However, lightly-doped-drain TFTsusually require relatively complicated fabrication processes thatinclude additional photo-masking and impurity doping steps to form theoffset regions.

[0012] Moreover, TFTs according to FIGS. 2 and 3 also have relativelyhigh leakage current because of contaminants that cross the interfacebetween the semiconductor layer and the buffer layer during thefabrication of the TFT.

[0013] Therefore, an improved thin film transistor, and a method offabricating such a thin film transistor, having decreased leakagecurrent would be beneficial.

SUMMARY OF THE INVENTION

[0014] Accordingly, the present invention is directed to thin filmtransistors, and methods of fabricating such thin film transistors, thatreduce the leakage current problems found in the related art.

[0015] An object of the present invention is to provide a thin filmtransistor, and a fabricating method thereof, having decreased leakagecurrent achieved by reducing the electric field from the boundary of thedrain region when an OFF voltage is applied, wherein the electric fieldis reduced by a doping step wherein impurities having a generallyGaussian distribution are formed such that the projection range Rp islocated away from the surface of the semiconductor layer, and by havingthe impurities that remain at the surface of the semiconductor layer ata predetermined concentration which is relatively small.

[0016] Another object of the present invention is to provide a thin filmtransistor and a fabricating method thereof which has a smallsource/drain resistance produced by increasing the depth of Rp so as toreduce the surface impurities concentration, while maintaining theimpurities above a predetermined level.

[0017] A further object of the present invention is to provide a thinfilm transistor and a fabricating method thereof which preventscontaminants from acting as a source of back channel current bycompensating the amount of contaminants penetrating between a bufferlayer and a semiconductor layer during the fabrication of a TFT bycontrolling the doping condition so as to have Rp located near or in thebuffer layer.

[0018] Additional features and advantages of the present invention willbe set forth in the description that follows, and in part will beapparent from that description and/or the drawings, or may be learned bypractice of the invention. The objectives and other advantages of thepresent invention will be realized and attained by the structurediscussed in the description and in the claims, as well as in thedrawings.

[0019] To achieve these and other advantages of the present invention,as embodied and broadly described herein, there is provided a thin filmtransistor having a semiconductor layer having source and drain regionsdefined by doped impurities, a gate insulating layer and a gateelectrode, wherein the impurities in the source and drain regions areimplanted into the semiconductor layer such that the resulting impurityconcentration profile has a projected range Rp at a depth that is awayfrom the surface of the semiconductor layer, and wherein the impuritiesare distributed so as not to have a maximum concentration at the surfaceof the semiconductor layer.

[0020] In another aspect, the present invention relates to a method offabricating a thin film transistor having a semiconductor layer withsource, drain, and channel regions, a gate insulating layer over thesemiconductor layer, and a gate electrode over the gate insulatinglayer. Those source and drain regions are defined by impurity doping thesemiconductor layer, with the impurity doping carried out by settingdoping impurity kinetic energies such that the doping impuritiesdistribute into the semiconductor layer such that they do not have amaximum concentration at the surface of the semiconductor layer, andsuch that the impurities are implanted into the semiconductor layer soas to have a projected range Rp that is located at a depth that is awayfrom the surface of the semiconductor layer.

[0021] In another aspect, the present invention relates to fabricating athin film transistor having a buffer layer, a semiconductor layer onthat buffer layer, a gate insulating layer over the semiconductor, and agate electrode over the gate insulating layer. That semiconductor layerincludes source and drain regions that are defined by impurity dopingthe semiconductor layer, wherein the impurity doping is carried out bysetting doping impurity kinetic energies such that the impuritiesdistribute into the semiconductor layer such that they are implantedinto the semiconductor layer so as to have a projected range Rp locatedat a depth that is away from the surface of the semiconductor layer, andsuch that the impurity concentration at the surface of the semiconductorlayer is less that the impurity concentration at the interface betweenthe semiconductor layer and the buffer layer.

[0022] It is to be understood that both the foregoing generaldescription and the following detailed description are exemplary andexplanatory and are intended to provide further explanation of theinvention as claimed.

BRIEF DESCRIPTION OF THE DRAWING

[0023] The accompanying drawings are included to provide a furtherunderstanding of the invention, are incorporated into and constitute apart of this specification, illustrate embodiments of the invention,and, together with the description, serve to illustrate the principlesof the invention.

[0024] In the drawings:

[0025]FIG. 1 is a graph of a Gaussian distribution of doping impurities;

[0026]FIG. 2 illustrates a cross-sectional view of a prior art TFT thatis doped with impurities according to a related art;

[0027]FIG. 3 presents a graph of the doping impurity concentration ofthe TFT illustrated in FIG. 2;

[0028]FIG. 4 illustrates a cross-sectional view of a TFT according tothe principles of the present invention;

[0029]FIG. 5 is a graph of the impurity concentration of the TFTillustrated in FIG. 4;

[0030]FIG. 6A to FIG. 6H show graphs of doping impurity concentrationsverses depth for various impurity acceleration voltages; and

[0031]FIG. 7A to FIG. 7D show graphs of the transfer curves of TFTsfabricated using various impurity acceleration voltages.

DETAILED DESCRIPTION OF ILLUSTRATED EMBODIMENTS

[0032] Reference will now be made in detail to illustrated embodimentsof the present invention.

[0033]FIG. 4 and FIG. 5 present various illustrations of a TFT that isin accord with the principles of the present invention. FIG. 4illustrates a cross-sectional view of that TFT, while FIG. 5 presents agraph of doping impurity concentration verses depth (into asemiconductor layer) of that TFT. Referring now to FIG. 4, asemiconductor layer 41 is formed on a buffer layer 40 that is over asubstrate 400. Over the center of the semiconductor layer 41 is a gateinsulating layer 42 and a gate electrode 43. At one side of thesemiconductor layer 41 is a source region 41S that is doped withimpurities, while the other side of the semiconductor layer has a drainregion 41D that is also doped with impurities. Below the gate insulatinglayer 22 is an undoped channel region 41C. Generally, the semiconductorlayer 41 is doped with impurities by using the gate electrode 43 as amask.

[0034] As previously mentioned, doping impurities within a semiconductorlayer typically follow a Gaussian distribution. As the accelerationvoltage applied to the doping particles increases, so does thedistribution deviation ARp. Thus, it is possible to adjust the impurityconcentration at various locations within the semiconductor layer byadjusting the acceleration voltage. This enables the manipulation of Rpand the doping concentration of impurities.

[0035] In the present invention, as shown in the FIG. 5, impurity dopingis carried out so as to locate Rp away from the surface of thesemiconductor layer 41. Indeed, it is beneficial to locate Rp below themiddle of the semiconductor layer. For example, it is beneficial tolocate Rp 500 Å to 1000 Å below the top surface of the semiconductorlayer when the semiconductor layer has a thickness between 900 Å to 1800Å. Thus, the location of Rp, as shown in FIG. 5, is controlled so as tobe well-below the surface of the semiconductor layer 41. Furthermore,doping is also controlled such that the impurity concentration near thesurface of the semiconductor layer 41 is at a predeterminedconcentration, which, while depending on process conditions, isgenerally lower than 10¹⁸-10²⁰/cm³.

[0036] As shown in FIG. 5, the doping can be carried out such that thedoping impurity concentration at the interface between the semiconductorlayer 41 and the buffer layer 40 is actually higher than the dopingimpurity concentration at the surface of the semiconductor layer 41. Forinstance, the impurity concentration at the interface between thesemiconductor layer 41 and the buffer layer 40 may be greater than10¹⁹/cm³ while the impurity concentration at the surface of thesemiconductor layer may be less than 10¹⁹/cm³.

[0037] A TFT that is in accord with the principles of the presentinvention can have less leakage current when an OFF voltage is appled toit than the TFT illustrated in FIGS. 2 and 3. This is believed to bebecause a TFT according to the present invention has fewer impuritiesremaining at the surface of the semiconductor layer to impact theelectric field near the drain region when the OFF voltage is applied.

[0038] Furthermore, the principles of the present invention preventcontaminants from aiding back channel current. This is achieved bycompensating for the contaminants penetrating the interface between thebuffer layer and the semiconductor layer by controlling the dopingconditions to locate Rp at or near the buffer layer.

[0039] The principles of the present invention have been verified. Forexample, FIGS. 6A to 6H present graphs of doping impurity concentrationsversus depth in a semiconductor layer as doping impurity accelerationvoltages are changed. In the illustrated Figures the doping impurity isboron having a dose set to 2×10¹⁵/cm². The graphs illustrate dopingimpurity concentrations versus depth using impurity accelerationvoltages of 10 kV, 20 Kv, 30 kV, 40 kV, 50 kV, 60 kV, 70 kV and 80 kVrespectively.

[0040] As shown in the FIGS. 6A to 6H, the larger the accelerationenergy becomes, the deeper Rp becomes. Additionally, when impuritydoping is carried out at the same dose, the impurity concentration atthe surface of the semiconductor layer varies in accordance with thelocation of Rp. Therefore, the principles of the present inventionenable one to control the doping impurity concentration at variousdepths below the surface of the semiconductor layer by manipulating Rpand the doping concentration of the impurity.

[0041]FIGS. 7A to 7D present transfer curves of TFTs that are inaccordance with the principles of the present invention. Specifically,those graphs are of p type TFTs, wherein boron having a dose set to3×10¹⁵/cm² is used as the doping impurity, and in which doping impurityacceleration voltages of 10 kV, 25 kV, 35 kV and 45 kV, respectively,are used.

[0042] As shown in FIGS. 7A to 7D, leakage current when an OFF voltageis applied is generally reduced as the impurity acceleration voltageincreases. For example, a TFT fabricated by doping using a dopingimpurity acceleration voltage of 10 KV has an OFF current of 341 pA withan OFF gate voltage of 4.2V. In contrast, a similar TFT fabricated byimpurity doping at an impurity acceleration voltage of 45 kV, providesan OFF current of 104 pA stet OFF gate voltage of 4V. This is areduction in leakage current of 67.5%.

[0043] The results imply that the OFF current is reduced as a result ofa decreased electric field near the boundary of the drain region duringthe OFF state. The above results also indicate that the OFF current isreduced by a decrease in the electric field between the gate and thedrain during the OFF state when the surface of the semiconductor layeris doped lightly with impurities. Moreover, the results further indicatethat boron ions implanted so as to locate Rp near the bufferlayer/semiconductive layer interface enables the reduction of a“backside current source” generated by contaminates that cross theinterface during the fabrication of a TFT. Furthermore, although theillustated test results relate to p type TFTs doped with boron ions, theprinciples of the present invention do not depend on the specificstructure illustrated or to the conductive type of TFT. For example, OFFcurrent reduction is also present in dual gate structures that are inaccord with the principles of the present invention.

[0044] As mentioned in the above description, the present inventionenables the reduction in OFF current by controlling the dopingimplantation energy during the fabrication of a TFT of a generalstructure.

[0045] Accordingly, the principles of the present invention enables areduction in OFF state leakage current without introducing alightly-doped-drain structure.

[0046] TFTs used as switching devices in liquid crystal displays willparticularly benefit from the principles of the present invention.

[0047] It will be apparent to those skilled in the art that variousmodifications and variation can be made in the present invention withoutdeparting from the spirit or scope of the invention. Thus, it isintended that the present invention covers the modifications andvariations of this invention provided they come within the scope of theappended claims and their equivalents.

What is claimed is:
 1. A thin film transistor having a semiconductorlayer, a gate insulating layer adjacent said semiconductor layer, and agate electrode over a portion of said gate insulating layer, saidsemiconductor layer further having a source region doped with animpurity and a drain region doped with an impurity, wherein saidimpurities of said source region and said drain region are implantedinto said semiconductor layer so as to have an impurity concentrationprofile with a projected range Rp at a depth below a surface of saidsemiconductor layer, and wherein said impurities have a maximumconcentration below said surface.
 2. The thin film transistor accordingto claim 1, wherein said impurities at said surface have a concentrationless than 10¹⁸/cm².
 3. The thin film transistor according to claim 1,wherein said impurities at said surface have a concentration less than10²⁰/cm².
 4. The thin film transistor according to claim 1, wherein saiddepth is greater than 500 Å.
 5. The thin film transistor according toclaim 4, wherein said depth is less than 1000 Å.
 6. The thin filmtransistor according to claim 5, wherein said impurities at said surfacehave a concentration less than 10¹⁸/cm².
 7. The thin film transistoraccording to claim 5, wherein said impurities at said surface have aconcentration less than 10²⁰/cm².
 8. The thin film transistor accordingto claim 1, wherein said semiconductor layer interfaces with a bufferlayer.
 9. The thin film transistor according to claim 8, wherein a donerimpurity concentration at said interface with said buffer layer isgreater than a doner impurity concentration at said surface.
 10. Amethod of fabricating a thin film transistor having a semiconductorlayer with a source region, a drain region defined by impurity doping, agate insulating layer, and a gate electrode, wherein said impuritydoping is carried out by setting an impurity acceleration voltage, usingsaid impurity acceleration voltage to accelerate impurity particles, anddirecting the acceleration impurity particles onto a surface of saidsemiconductor layer, wherein said impurity acceleration voltage causessaid impurities to distribute into said semiconductor layer such that amaximum concentration of impurities forms below said surface, andwherein said impurities form a doping impurity concentration profilehaving a projected range Rp below said surface.
 11. The method offabricating a thin film transistor according to claim 10, wherein saidprojected range Rp is more than 500 Å below said surface.
 12. The methodof fabricating a thin film transistor according to claim 11, whereinsaid projected range Rp is less than 1000 Å below said surface.
 13. Themethod of fabricating a thin film transistor according to claim 10,wherein said impurity acceleration voltage causes impurities at saidsurface to have concentration less than 10¹⁸/cm²
 14. The method offabricating a thin film transistor according to claim 10, wherein saidimpurity acceleration voltage causes impurities at said surface to haveconcentration less than 10²⁰/cm².
 15. A method of fabricating a thinfilm transistor, comprising: forming a buffer layer on a substrate;depositing a semiconductor layer on said buffer layer such that aninterface is formed between said buffer layer and said semiconductorlayer, wherein said semiconductor layer has an exposed surface;accelerating doping impurity particles using a predetermined impurityacceleration voltage; and directing said accelerationed doping impurityparticles onto said exposed surface; wherein said predetermined impurityacceleration voltage causes said doping impurity particles to distributeinto said semiconductor layer such that said doping impurities have amaximum concentration below said exposed surface and such that saiddoping impurities form a doping impurity concentration profile having aprojected range Rp below said exposed surface.
 16. The method offabricating a thin film transistor according to claim 15, furtherincluding the step of forming a gate insulating layer on saidsemiconductor layer and the step of forming a gate electrode on saidgate insulating layer.
 17. The method of fabricating a thin filmtransistor according to claim 15, wherein said projected range Rp ismore than 500 Å below said exposed surface.
 18. The method offabricating a thin film transistor according to claim 17, wherein saidprojected range Rp is less than 1000 Å below said exposed surface. 19.The method of fabricating a thin film transistor according to claim 15,wherein said impurity acceleration voltage causes impurities at saidsurface to have concentration less than 10¹⁸/cm²
 20. The method offabricating a thin film transistor according to claim 15, wherein saidimpurity acceleration voltage causes impurities at said exposed surfaceto have concentration less than 10²⁰/cm².
 21. The method of fabricatinga thin film transistor according to claim 15, wherein said donerimpurities have a concentration at said exposed surface that is lessthat a doner impurity concentration at said interface.